Many-core embedded systems (MES) are moving towards the integration of hundreds cores on a single chip and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication becomes power and performance bottleneck in future MES. Network-on-Chip (NoC) architecture has been proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoC provides an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications using the full power of NoC-based MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that, for managing many-core resources, contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing scalable and faultless OSs will be a tremendous challenge in future MES. The goal of this workshop is to bring together the researchers from academia and the experts from industry to present and discuss innovative ideas and solutions in the design, modeling, prototyping, programming, and implementation of MES.