The Program Committee cordially invites you to participate and submit your contribution to DFT 2016. The conference topics include (but are not limited to) the following:

• Yield Analysis and Modeling
  Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.

• Testing Techniques
  Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.

• Design For Testability in IC Design
  FPGA, SoC, NoC, ASIC, microprocessors.

• Error Detection, Correction, and Recovery
  Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques, architectural-specific techniques, system-level strategies.

• Dependability Analysis and Validation
  Fault injection techniques and environments; dependability characterization; aging modeling and analysis.

• Repair, Restructuring and Reconfiguration
  Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.

• Defect and Fault Tolerance
  Reliable circuit/system synthesis; radiation hardened and/or tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors; aging management and recovery strategies.

• Fail-Safe Design for Critical Applications
  Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.

• Emerging Technologies
  Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.

• Design for Security
  Fault attacks, fault tolerance-based counter-measures, Scan-based attacks and counter-measures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.