The International workshop on "Data-Flow Models (DFM) for extreme scale computing" was held in six consecutive years in conjunction with the PACT conference. The purpose of DFM continues being to bring together those researchers interested in novel computational models based on Data-Flow principles of execution. The switch to multi-core systems has raised concurrency to the level of a major issue if we are to use the increasing number of cores in a chip. 
In the past five decades, sequential computing dominated the computer architecture landscape because designers were successful at building faster and faster computers by solely relying on improvements on fabrication technologies and architectural/organization optimizations. The most severe limitation of the sequential model, namely its inability to tolerate long memory latencies has slowed down the performance gains. This phenomenon is the ubiquitous Memory Wall. While various mechanisms have been implemented to overcome the wall (such as extremely efficient hardware prefetch support for example), they only add to another wall that hampers highly efficient execution of programs and modern chip design: the Power Wall. Power considerations and heat dissipation issues have forced manufacturers to switch to multiple cores per chip and thus move into the concurrency era. 
New concurrent models/paradigms are needed in order to fully utilize the potential of multi-core chips. The data-flow model is a formal model that can handle concurrency and tolerate memory and synchronization latencies. Data-Flow inspired systems could also be simpler and more power efficient than conventional systems. 
Recent work has shown that the data-flow principles can be used to develop systems that can outperform systems based on conventional techniques. Thus, it is time to revisit data-driven computation and bring it to the multi-core and extreme scale computing.